1. Field of the Invention
The present invention concerns design of integrated circuits (ICs) and particularly relates to a faster method for designing an integrated circuit by delaying selection of specific cells.
2. Description of the Prior Art
Current integrated circuits frequently contain hundreds of thousands or millions of interconnected electronic devices. Designing an integrated circuit so that such a large number of devices interact to provide the desired functionality can be a difficult task. Moreover, due to the increasing demand for quick turnaround-time application-specific integrated circuits, it is desired that the design process be completed as quickly as possible. Accordingly, a highly structured multi-step process has evolved. FIG. 1 illustrates a flow diagram for explaining one example of such a conventional integrated circuit design technique.
Initially, an IC design specification is produced in step 20. From that specification, a technology-independent circuit description is generated in step 22. Thereafter, in synthesis step 24 a gate-level description is synthesized based on the input technology-independent description.
Conventionally, synthesis step 24 typically inputs a circuit description in a hardware description language (HDL) and/or in a register transfer language (RTL). From that description, specific electronic components (or "cells") are selected from a technology library 40 so as to implement the required functionality. Because actual physical devices are selected in this step, actual performance criteria typically are considered when making these selections. Thus, for example, if an AND gate is required, then synthesis step 24 will select from among a number of AND gates in the technology library 40 based on timing considerations. In general, timing will be a function of output drive strength and the amount of load required to be driven by the gate. Thus, higher drive strength gates typically will have lower delay times for a given load than will lower drive strength gates.
In addition to selecting from among components having the same functions but different drive strengths, fundamental architectural decisions also are made in synthesis step 24. In fact, these two types of decisions are actually interrelated, since one architectural choice may be acceptable in connection with higher drive strength gates, but would produce timing errors when used in connection with lower drive strength gates. Accordingly, synthesis step 24 ordinarily requires a significant amount of processing time to obtain an optimal combination of these interrelated considerations.
As noted above, synthesis step 24 attempts to meet the timing constraints specified by the design; timing, in turn, typically is a function of the amount of load each gate must drive. In this regard, load generally consists of gate load and wire load. Because synthesis step 24 is selecting the gates, it usually can accurately predict the amount of gate load. However, wire load ordinarily must be estimated, typically by using a generic wire load model.
The output of synthesis step 24 is a netlist, which specifies particular components and also specifies all required interconnections between those components. In placement step 26, the components in the netlist are laid out on the surface of the integrated circuit chip. In step 28, connections are routed between the individual components. Based on that routing, step 30 determines routing characteristics, such as wire load. Such wire load models historically have not been very accurate.
In step 32, it is determined whether timing errors exist. Such errors exist mainly because actual wire load often varies from the wire load estimated using the generic wire load model in synthesis step 24. If such errors are in fact present, incremental synthesis is attempted in step 34 to resolve those timing errors. Such incremental synthesis attempts to achieve timing closure by making relatively minor changes in the design. Incremental synthesis step 34 might, for example, substitute higher drive strength gates for existing gates in the design in an attempt to eliminate those timing errors.
In step 36, it is then determined whether any errors still exist which can not be corrected by the relatively minor changes made during incremental synthesis step 34. If any such errors still exist, then processing returns to step 24 in order to perform full synthesis once again in an attempt to correct such errors. It is noted that re-execution of full synthesis is often required in this conventional technique due to poor architectural decisions made during the initial synthesis.
For example, assume that an adder is required. Based on the generic wire load model information, initial synthesis might have determined that by using sufficiently high drive-strength cells timing constraints could be met by using a relatively slow ripple-adder structure. However, when routing has been completed, it might be determined that wire load is actually much higher than the wire load model had predicted. In fact, in these conventional techniques, it is not uncommon to discover that actual loads are 10 to 20 times greater than predicted by the model. Because high drive-strength components were used initially, there might not be available sufficiently higher drive-strength components to accommodate such a substantially higher wire load. Therefore, the only option might be to re-execute full synthesis utilizing the new information. Upon such re-execution, the synthesis step might select a faster adder circuit implementation.
In fact, due to the inaccuracies of current wire load models, many such design changes typically will be required after the first pass. Therefore, upon completion of the second full synthesis, the design might be so significantly different that the placement, routing and resulting routing characteristics (such as wire loads) also end up being significantly different than in the first pass. As a result, loop 38 may need to be repeated several times until all timing errors have been eliminated (i.e., timing closure achieved).
What is needed, therefore, is a more efficient process for designing an integrated circuit. In particular, it would be desirable to have a process that both completed initial synthesis faster and reduced the number of iterations required to be performed. Previous efforts to solve these problems mainly have focused on improving the wire load model used. However, for the most part, these efforts have not achieved a great degree of success.